(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a method used to form a metal silicide layer on a source/drain region of a metal oxide semiconductor field effect transistor, (MOSFET).
(2) Description of Prior Art
The semiconductor industry is continually striving to improve the performance of semiconductor devices. This objective has in part been satisfied via micro-miniaturization, or the ability to fabricate semiconductor devices with sub-micron features. Advances in specific fabrication disciplines such as photolithography and dry etching have allowed the attainment of devices with sub-micron features to be realized. Sub-micron regions result in areas of decreased capacitance, when compared to counterparts fabricated with larger features, thus reducing the capacitance component of the device RC delay. In addition the resistance component of the RC factor has in part been addressed via resistance decreases in word line and bit line resistance, via the use of metal silicide layers on gate structures as well as on source/drain regions. One method of forming metal silicide layers on these regions has been via use of a Self-ALIgned metal siliCIDE, (salicide), procedure, in which a blanket metal is deposited, annealed to form metal silicide on regions in which the metal layer overlaid silicon, (top surface of gate structure and source/drain region), followed by the removal of unreacted metal from insulator surfaces, such as insulator spacers located on the sides of the gate structure. However one problem encountered with the salicide procedure is the inability to completely remove unreacted metal from the insulator spacers, resulting in gate to substrate leakage or shorts. In addition prolonged anneal cycles, used to insure salicide reaction can result in the formation of metal silicide ribbons on the surface of the insulator spacers, extending from the gate structure to source/drain regions, again resulting in yield loss in terms of gate to substrate leakage or shorts.
The present invention will describe a procedure for forming metal silicide on source/drain regions via implantation of metal ions, only into the source/drain region, thus eliminating the risk of forming ribbons, or leaving unreacted metal, on the sides of the insulator spacers, sometimes encountered with the salicide procedure. Prior art, such as Fazan et al, in U.S. Pat. No. 6,087,700, describe a method of forming a metal silicide layer on a blanket polysilicon layer, prior to defining the metal silicidexe2x80x94polysilicon gate structure. That prior art however does not describe this present invention in which metal silicide is formed only on a source/drain region, via implantation of metal ions, only into the source/drain region.
It is an object of this invention to form a metal silicide layer only on a source/drain region of a MOSFET device.
It is another object of this invention to implant metal ions into a source/drain region of a MOSFET device.
It is yet another object of this invention to perform an anneal cycle to form metal silicide on the source/drain region, via reaction of the implanted metal ions and silicon, available from the source/drain region.
It is still yet another object of this invention to selectively remove unreacted metal ions from the surface of the metal silicide layer.
In accordance with the present invention a method of forming metal silicide on a source/drain region of a MOSFET device, is described. After formation of a silicon dioxide gate insulator layer, a polysilicon or polycide layer is deposited, followed by the deposition of a dielectric layer. Definition of a gate structure, capped with the dielectric layer, is followed by formation of a lightly doped source/drain, (LDD) region, in a region of the semiconductor substrate not covered by the capped gate structure. After formation of insulator spacers on the sides of the capped, gate structure, a heavily doped source/drain region is formed in a region of the semiconductor substrate not covered by the capped gate structure or by the insulator spacers. Metal ions are next implanted into the heavily doped source/drain region, followed by an anneal procedure, used to form the desired metal silicide layer. Unreacted metal ions are then selectively removed from the top surface of the metal silicide layer. An optional second anneal cycle can next be performed to create a lower resistance phase of the metal silicide layer.